Stories from the ZeroRISC team — product announcements, research, partnerships, and perspectives on open-silicon security.
In this episode of our blog post series on hardening PQC for Pavona's asymmetric cryptography coprocessor (ACC), we describe our DPA-hardened implementation of the post-quantum signature scheme ML-DSA supporting all parameter sets (44, 65, and 87).
Read post →In this blog post on hardening PQC for Pavona's Asymmetric Cryptography Coprocessor (ACC), we cover why masking is needed, how it applies to the post-quantum key-encapsulation mechanism ML-KEM, and what our implementation looks like. We build on Pavona's pre-existing ML-KEM implementation.
Read post →In this post, we’ll explain a new method to benchmark ML-DSA signing with relatively few test inputs. We can get a better measurement from as few as 1 or 2 specially-selected test inputs as we would get from 100 random tests. You can find the code here .
Read post →This post follows on from the recent cross-post from our research collaborators at MPI-SP about their innovative design for ML-KEM and ML-DSA acceleration. Today, we’ll focus on what happened in between the researchers creating the initial implementation and now, when we have lattice cryptography support derived…
Read post →We describe extensions based on the OpenTitan Big Number (OTBN) coprocessor to enable very efficient support for recently standardized lattice-based post-quantum crypto systems, achieving speed-ups of a factor of 6--9x compared to the baseline. The resulting extende d design for an Asymmetric Cryptography…
Read post →This post describes design choices we made in developing the cryptolib embedded cryptographic library.
Read post →This post is the second in a two-part series about recently implemented optimizations to speed up performance of our open-source, embedded RSA implementation. Read part one here . This post will cover the actual implementation of RSA CRT key generation and modular exponentiation. Our implementation focuses on…
Read post →This post is the first of a two-part series describing recent improvements to make our embedded RSA software (originally developed in the OpenTitan codebase) production ready, leading to a huge speedup for core operations.
Read post →This blog post covers ZeroRISC’s recent contributions implementing one-time programmable (OTP) memory zeroization to achieve FIPS 140-3 compliance. We did this in partnership with Rivos Inc , using the code at git hash 032df24 , as part of our commitment to aligning open silicon with important industry security…
Read post →This blog post is the second in our two-part summer internship series. Following Beshr’s great work on porting Enabling Position-Independent Code and Dynamic Memory Management in ZeroRISC OS, Yeabsira tackled porting OpenTitan’s interconnect from TL-UL to AXI.
Read post →This Summer, ZeroRISC had the pleasure of hosting two Summer interns in our Boston office. This blog post is the first in a two-part series highlighting their work tackling challenging real-world problems at the intersection of hardware and software.
Read post →On July 4th, ZeroRISC and the Tock secure embedded OS development team jointly presented a full-day tutorial on secure firmware design for hardware roots of trust (HWRoTs) using Tock. This tutorial spotlighted Tock's memory protection, process management, and compiler-derived kernel isolation guarantees, providing…
Read post →This is part 3 of 3 in an experience report about implementing SPHINCS+ (aka SLH-DSA) for secure boot in OpenTitan root of trust (RoT) chips. SPHINCS+ is a post-quantum secure signature algorithm and one of the four winners of NIST’s post-quantum cryptography competition; the final standard was recently released as…
Read post →This is part 2 of 3 in an experience report about implementing SPHINCS+ (aka SLH-DSA) for secure boot in OpenTitan root of trust (RoT) chips. SPHINCS+ is a post-quantum secure signature algorithm and one of the four winners of NIST’s post-quantum cryptography competition; the final standard was recently released as…
Read post →This is part 1 of 3 in an experience report about implementing SPHINCS+ (aka SLH-DSA) for secure boot in OpenTitan root of trust (RoT) chips. SPHINCS+ is a post-quantum secure signature algorithm and one of the four winners of NIST’s post-quantum…
Read post →Stay tuned for future posts about the exciting contributions we’ve been making to OpenTitan, other open-source projects, and the widespread security community.
Read post →Research, engineering write-ups, and the occasional product update. No marketing.