Open silicon security, end to end — from design through manufacturing to every field update.
When component trust is fragmented, bulletproof security requires an end-to-end solution — not five vendors and a prayer.
A single gap — design, factory, or deployment — causes delays, recalls, blocked market entry, and outages that hit revenue and reputation.
Built with certification-aligned open-source silicon; built transparently to meet and exceed certification requirements for demonstrable trust across the full lifecycle.
Most implementations are patchwork — different vendors at every step in the supply chain, poor integration, undermaintained, built to the minimum spec.
ZeroRISC is your end-to-end partner for deploying secure open silicon at scale. Start anywhere, grow into the full stack.
Modern repositories, continuous integration for silicon, and post-quantum-ready chip IP. The tools and silicon a modern chip program needs — not a dusty closed-source design.
Architectural decisions that compound over time — not things a competitor can bolt on in the next release.
Every gate inspectable. No black boxes, no trust-the-vendor. Built on the only production-grade open-source silicon root of trust.
Hardware-accelerated ML-KEM, ML-DSA, and SLH-DSA. PQC secure boot has been in production since first chip samples — not a roadmap item.
Design-time IP, factory provisioning, lifecycle management — one team, one roadmap, zero integration gaps across five different vendors.
Built for FIPS 140-3, EU CRA, Common Criteria PP-0117 & PP-0084, and more. Reduce compliance effort — don't add to it.
The same trust stack underpins phones, vehicles, industrial controllers, and chiplets — delivered with the compliance story each industry needs.
Access carrier and payment markets. Reduce design spins. Ship faster with a certifiable RoT.
Post-quantum cryptography ready. Firmware OTA without the warranty and recall risk.
Continuous vulnerability management across billions of long-lived, low-touch devices.
Per-chiplet attestation, trust across mixed-vendor packages, hyperscaler-ready fleets.
In this post, we’ll explain a new method to benchmark ML-DSA signing with relatively few test inputs. We can get a better measurement from as few as 1 or 2 specially-selected test inputs as we would get from 100 random tests. You can find the code here .
Read post →This post follows on from the recent cross-post from our research collaborators at MPI-SP about their innovative design for ML-KEM and ML-DSA acceleration. Today, we’ll focus on what happened in between the researchers creating the initial implementation and now, when we have lattice cryptography support derived…
Read post →We describe extensions based on the OpenTitan Big Number (OTBN) coprocessor to enable very efficient support for recently standardized lattice-based post-quantum crypto systems, achieving speed-ups of a factor of 6--9x compared to the baseline. The resulting extende d design for an Asymmetric Cryptography…
Read post →Whether you're designing a chip, provisioning a factory, or managing a fleet already in the field — we'll meet you where you are.